1. Field
The present invention relates to a method of manufacturing a semiconductor device that includes a drift layer including an alternating-conductivity-type-layer. The alternating-conductivity-type-layer includes an n-type column and a p-type column, both extending in perpendicular to the major surface of a semiconductor substrate. The n-type column and the p-type column are arranged alternately and repeatedly in parallel to the major surface of the semiconductor substrate such that the n-type column and the p-type column are adjoining to each other. Hereinafter, the alternating-conductivity-type-layer is sometimes referred to as a “super-junction structure,” and the semiconductor device including an alternating-conductivity-type-layer is referred to as a “super-junction semiconductor device.”
2. Description of the Related Art
A super-junction MOSFET that is a vertical power MOSFET including a drift layer provided with a super-junction structure is know as one of the super-junction semiconductor devices.
Even if the impurity concentrations in the p-type and n-type columns constituting the drift layer provided with a super-junction structure in the super-junction semiconductor device are set to be higher than the impurity concentrations in the usual power semiconductor device of the same breakdown voltage class, depletion layers will expand from the pn-junction between the p-type and n-type columns to both sides in the OFF-state of the device. The depletion layers expanding from the pn-junction between the p-type and n-type columns to both sides in the OFF-state of the device deplete the p-type and n-type columns at a low electric field strength. Therefore, it is possible to provide the super-junction semiconductor device with a higher breakdown voltage. For providing the super-junction semiconductor device with a higher breakdown voltage, the charge balance between the p-type and n-type columns is important. In other words, it is desirable for the p-type and n-type columns to be charged electrically in the same extent.
As a result, the super-junction semiconductor device facilitates reducing the ON-state resistance, that is in the tradeoff relation against the breakdown voltage, to a value not only low enough to transcend the limit caused by the tradeoff relation but also low enough to transcend the theoretical limit of the material.
Japanese Unexamined Patent Application Publication No. 2001-119022 describes a method well known to persons skilled in the art for manufacturing the super-junction structure.
The method described in JP 2001-119022 includes the step of growing an epitaxial layer above a semiconductor substrate exhibiting low electrical resistance, the step of patterning a resist, and the steps of implanting p-type ions and n-type ions for forming a thin p-type column and a thin n-type column. This method repeats the step of growing, the step of patterning, and the steps of implanting multiple times until p-type columns of a desired thickness and n-type columns of the desired thickness are obtained. For forming the p-type columns and the n-type columns, both thick in perpendicular to the substrate surface, in an excellent fashion, it is necessary to lay a thin p-type column exactly on the p-type column already formed and a thin n-type column exactly on the n-type column already formed. In other words, it is necessary to align the p-type columns and the n-type columns with high positioning accuracy.
Now the conventional method of manufacturing a super-junction structure, that repeats the step of epitaxial growth, the step of resist patterning, and the steps of ion-implantation multiple times for stacking p-type columns and n-type columns in perpendicular to the substrate surface with a desired positioning accuracy, will be described below.
First, a silicon epitaxial layer (first layer) is grown for several μm above a silicon substrate exhibiting low electrical resistance and an alignment mark used in patterning the resist for ion-implantation is formed. The alignment mark is formed on a scribe line using a trench. Phosphorus ions are implanted into the entire epitaxial layer. A resist opening for defining a boron-ion-implanted region is formed by photolithography and boron ions are implanted through the resist opening. The resist is removed and a silicon epitaxial layer (second layer) is grown. Then, phosphorus ions are implanted into the entire second layer. Then, a resist patterning for defining the boron-ion-implanted region again is conducted. The initial alignment mark formed in the first layer surface and transferred to the second layer surface is used for the alignment mark for pattering the resist to position a boron-ion-implanted region in the second layer exactly on the boron-ion-implanted region in the first layer.
As described above, the step of epitaxial growth, the step of resist patterning, and the steps of ion-implantation are repeated multiple times for forming an alternating-conductivity-type-layer including a p-type column and an n-type column, positioned at the respective right positions, having a desired thickness, arranged alternately and repeatedly in parallel to the substrate surface such that the p-type column and the n-type column are adjoining to each other. The alternating-conductivity-type-layer forms a super-junction structure.
Japanese Unexamined Patent Application Publication No. Hei. 5 (1993)-343319 describes a method well known to persons skilled in the art for improving the accuracy of aligning the selectively-ion-implanted regions. The method described in JP 5-343319 relates to the alignment marks used in patterning the selectively-ion-implanted regions formed in the silicon epitaxial layers grown above a silicon substrate of low electrical resistance. The alignment marks are formed in the surfaces of the silicon epitaxial layers. This method forms a new alignment mark in the second layer at a position different from the alignment mark position transferred to the second layer from the first layer. The use of a new alignment mark in the second layer at a position different from the alignment mark position transferred to the second layer from the first layer improves the alignment accuracy as compared with the use of the alignment mark transferred from the first layer to the second layer.
JP 5-343319 also describes an etching method for sharpening the boundary of the transferred alignment mark blunted by every epitaxial layer growth to be clear enough for an effective next mask alignment.
Japanese Unexamined Patent Application Publication No. 2008-130919 describes the preferable use of KOH for an etchant that corrects to sharpen the blunted alignment mark boundary.
For forming the alignment mark in the second layer at a position different from the position, at which the alignment mark in the first layer is formed, to improve the alignment accuracy as described in JP 5-343319, it is necessary to add a new alignment step for forming the alignment mark in the second layer.
If the epitaxial layer growth rate is made to be low, the deformation or the bluntness caused on the alignment mark will be reduced. As a result, the transferred alignment mark in the second epitaxial layer surface transferred from the initial alignment mark is deformed or blunted only a little. Therefore, the transferred alignment mark is used without correction for the alignment on the second and subsequent epitaxial layers with high accuracy. In the device exhibiting a high breakdown voltage, the thick drift layer thereof is formed by laminating many epitaxial layers. If the epitaxial growth rate is set to be low, it will take a too long time to grow the epitaxial layers. Therefore, the low epitaxial growth rate is not preferable.
If an alignment mark is formed after every epitaxial layer growth, an alignment may be conducted with high accuracy and the epitaxial growth rate may be made to be high. However, it will be necessary to add many cumbersome alignment steps.
In view of the foregoing, it would be desirable to obviate the problems described above. It would be also desirable to provide a method of manufacturing a super-junction semiconductor device that facilitates increasing the epitaxial growth rate without increasing the manufacturing steps greatly.